Lists of elements used by SIDSC member companies to describe register details in their legacy documents.

Collating these lists will be used as a starting point for DITA specializations.

THIS PAGE HAS BEEN DEPRECATED

Please refer to http://www.oasis-open.org/apps/org/workgroup/dita-sidsc/document.php?document_id=27666 for the on-going work-in-progress.

Contributed by Duane Becker of IBM

Register Block Long Name
Register Block Short Name
Register Block Base Address	If offset is not used, then base address is the primary address.
Register Block Offset	Starting offset from Register Block Base Address for this register block.
Register Block Short Description	For what is this register block essentially used?
Register Block Long Description	Detailed accounting of the purpose of this register block.
Register Long Name
Register Short Name
Register Overall Description	This is a synopsis of a register, a brief "what is it used for". This might be used as a pop-up help for a debugger tool.
Register Detailed Description	This is a more detailed overall description of a register, but doesn't necessarily go into bit field-level descriptions.
Register Base Address
Register Offset Address
Register Access Type	(read/write, read/clear, read/set, write only, read only, etc)
Register Access Granularity	Byte, Word, Doubleword, etc.
Dimension 1	If this is a single register, then Dimension1 must equal 0. If the register is a linear array, this indicates how many rows there are in the array.
Dimension 2	If this is a single register or a linear array, this value must equal 0. If this is a rectangular array, this provides the number of columns.
Offset Delta 1	This indicates the incremental address offset to Dimension1 for each repeated row.
Offset Delta 2	This indicates the incremental address offfset to Dimension2 for each repeated column.
Reset Value	Hexadecimal without any special annunciators. The target post-processor would have to format it as required by the individual company's style. 'X' can be used to indicate that the register is not reset to any particular value.
Reset Triggers	A set of codes or values or bitnames or signalnames that indicate what actions can reset the register.
Endianness	"+": Bit 0 = MSb and bit numbers increment from left to right
	"-": Bit 0 = LSb and bit numbers decrement from left to right
Bitfield Long Name
Bitfield Short Name
Bit Numbers	Full list of comma-separated bit number to accomodate noncontiguous bit numbers of a collective field (for example, when a late top-metal-only design change adds a nonsequential bit to a field like [0:5,7] )
Starting Bit	Start and length are for contiguous bit fields. The incrementation of bit is established by Endianness (+ for IBM, - for Intel)
Field Length	Start and length are for contiguous bit fields. The incrementation of bit is established by Endianness (+ for IBM, - for Intel)
Field Description	The content normally used to describe the field.
Field Reset Value	The binary value to which this field is reset. X can be used to indicate NOT RESET.

Elements that align with SPIRIT IP-XACT.

Contributed by Jeremy Ralph of PDTi

PDTi

The following hierarchy of elements aligns with SPIRIT IP-XACT (with some naming differences and vendorExtensions). This contains a subset of info that is relevant for documentation purposes (before the math). A '*' indicates one or more of the element.

component
  name
  briefDescription
  description
  memoryMaps
    memoryMap*
      addressBlock*
        name
        briefDescription
        description
        baseAddress - relative to comp
        range
        width
        register*
          name
          briefDescription
          description
          dimension*
          addressOffset - relative to addressBlock
          size
          resetValue
          bitField*
            name
            briefDescription
            description
            bitWidth
            bitOffset - relative to rightmost bit
            access    - read-write, read-only, write-only, ...
            values*
              name
              value
              description

Contributed by Seth Park and Bob Beims of Freescale Semiconductor

Note: This model does not adequately address field states. In our documentation, we describe "what 0 means", for instance.